Interconnect Structure and Method for Forming Interconnect Structure

ABSTRACT

An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the interconnect structure, an α-phase inducing metal layer is introduced on a first Ta barrier layer of β phase to induce the subsequent deposition of Ta thereon into the formation of an α-phase Ta barrier layer. The subsequently deposited Ta barrier layer with a primary crystallographic structure of α phase has a lower Rc than that of the β-phase Ta barrier layer.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. Modern integrated circuits are made up of literally millions ofactive devices such as transistors and capacitors. Technologicaladvances in IC materials and design have produced generations of ICswhere each generation has smaller and more complex circuits than theprevious generation. These devices are initially isolated from eachother, but are later interconnected together through multiple metallayers to form functional circuits. As the IC becomes increasingly morecomplex, the interconnect structure also becomes more complex, resultingin increasing number of metal layers.

Typical interconnect structures include lateral interconnections, suchas metal lines (wirings), and vertical interconnections, such asconductive vias and contacts. Complex interconnects can limitperformance and the density of modern integrated circuits. Tantalum (Ta)has been used as a barrier layer material around copper conductors toblock the diffusion of conductive copper into a surrounding inter-layerdielectric (ILD) layer. Copper readily diffuses during operation in aphenomenon known as electromigration. Electromigration can producetendrils that can short adjacent conductive features. However, Ta asdeposited using current techniques exhibits a contact resistivity (Rc)that is much higher than that of copper. Thus, the Ta barrier layerlimits the overall line resistance. Hence, what is needed are structuresand methods of forming an interconnect structure with the blockingadvantage of Ta barrier layer without disadvantage of lower Rcperformance.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present disclosure are best understood from thefollowing detailed description when read with the accompanying figures.It is emphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIGS. 1 is a diagrammatic fragmentary cross-sectional side views of aninterconnect structure in a semiconductor device according to variousembodiments of the present disclosure.

FIG. 2 is a flowchart illustrating a method of fabricating aninterconnect structure according to various embodiments of the presentdisclosure.

FIGS. 3-9 are diagrammatic fragmentary cross-sectional side views of theinterconnect structure of FIG. 1 at various stages of fabricationaccording to various embodiments of the present disclosure.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof the invention. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Moreover,the formation of a first feature over or on a second feature in thedescription that follows may include embodiments in which the first andsecond features are formed in direct contact, and may also includeembodiments in which additional features may be formed interposing thefirst and second features, such that the first and second features maynot be in direct contact. Various features may be arbitrarily drawn indifferent scales for the sake of simplicity and clarity.

The singular forms “a,” “an” and “the” used herein include pluralreferents unless the context clearly dictates otherwise. Therefore,reference to, for example, a gate stack includes embodiments having twoor more such gate stacks, unless the context clearly indicatesotherwise. Reference throughout this specification to “one embodiment”or “an embodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the present disclosure. Therefore, theappearances of the phrases “in one embodiment” or “in an embodiment” invarious places throughout this specification are not necessarily allreferring to the same embodiment. Further, the particular features,structures, or characteristics may be combined in any suitable manner inone or more embodiments. It should be appreciated that the followingfigures are not drawn to scale; rather, these figures are intended forillustration.

As semiconductor device sizes continue to shrink, meeting conductivityrequirements as well as reliability in multiple metallizationfabrication has become increasingly more difficult. For example, theformation of an interconnect structure-which includes metal lines andconductive vias that interconnect metal lines from different layers-ofintegrated circuit (IC) devices generally requires a low resistance butalso a sound barrier layer blocking the conductive metal in theconductive vias diffusing into the ILD layer. To lower the RC delay inthe IC devices, the barrier layer also plays a significant role ingoverning the resistivity of interconnects.

In the known damascene process, the barrier layer and then a seed layerare deposited over the patterned dielectric layer surface before copperis introduced. Copper readily diffuses during operation in a phenomenonknown as electromigration than can produce tendrils that can shortadjacent conductive features. When in contact with silicon, copperdamages the semiconductor device operation. Thus, the barrier layer isneeded to prevent the copper from diffusing into the device region. Thinrefractory metals or metal nitrides are usually selected for the barrierlayer. Representative barrier layer materials include tantalum (Ta),tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titaniumand titanium nitride (Ta/TaN). Of all of these barriers, Ta showspromise for barriers and has been used as the material of a barrierlayer forming over a via hole to block the diffusion of conductive metalin the via hole into the ILD layer.

Tantalum exists as two phases, the low resistivity (15-30 μΩ·cm) α-phase(also referred to as the bcc or “body centered cubic” phase) and thehigher resistivity (150-200 μΩ·cm) β-phase (tetragonal structure). WhenTa is deposited by physical vapor deposition (PVD) process the β-phaseforms readily. However, Ta having a crystallographic structure of βphase exhibits less satisfactory property in contact resistance. Methodsof achieving the α-phase Ta are more difficult to reproduce and havebeen found to require heating the substrate, introduction of low levelimpurities into the film, and/or the use of specific base layers such asTaN between the dielectric and the Ta.

According to various embodiments of the present disclosure, an improvedinterconnect structure and a method for forming the interconnectstructure is disclosed that allows the interconnect structure to achievea lower Rc. To lower the Rc of the interconnect structure, an α-phaseinducing metal layer is introduced on a first Ta barrier layer of βphase to induce the subsequent deposition of Ta thereon into theformation of an α-phase Ta barrier layer. The subsequently deposited Tabarrier layer with a primary crystallographic structure of α phase has alower Rc than that of the β-phase Ta barrier layer.

To illustrate, FIG. 1 is a diagrammatic fragmentary cross-sectional sideviews of an interconnect structure in a semiconductor device accordingto various embodiments of the present disclosure. For reasons ofsimplicity, FIG. 1 may only illustrate a part of the interconnectstructure, and any intermediate layers between the illustrated portionof the interconnect structure and the substrate 110 are omitted. Theinterconnect structure may be a portion of a semiconductor device in awafer. FIG. 2 is a flowchart illustrating a method of fabricating aninterconnect structure according to various embodiments of the presentdisclosure. The operation will be explained in the cross-sectional sideviews of a portion of an interconnect structure from FIGS. 3 to 9 atvarious fabrication stages according to various embodiments of thepresent disclosure. It is understood that FIGS. 1, and 3 to 9 have beensimplified for a better understanding of the inventive concepts of thepresent disclosure.

FIG. 1 is an interconnect structure 100 that includes the substrate 110,the dielectric material layer 120 on the substrate 110, and a conductivefeature. The conductive feature has a copper-containing metal 160/170,the α-phase Ta barrier layer 150, the α-phase inducing metal layer 140,and the β-phase Ta barrier layer 130. The copper-containing metal is atleast partially and peripherally surrounded by the α-phase Ta barrierlayer 150. The α-phase Ta barrier layer 150 is peripherally surroundedby the α-phase inducing metal layer 140. Further, the α-inducing metallayer is peripherally surrounded by the β-phase Ta barrier layer 130.The copper-containing metal may include the seed layer 160 differentfrom or same as the second copper-containing metal 170 in composition.The seed layer is needed to provide the conductivity for theelectrochemical deposition reaction and to provide nucleation sites forthe subsequent copper electroplating. Usually, a thin copper layer isdeposited over the barrier layer to serve as the seed layer. As variousembodiments, the interconnect structure is a damascene or dual damascenestructure.

One skilled in the art will realize the formation details of themetallization layers. A metallization layer may be formed overlying theILD layer 120, which is a portion of conductive routs and has an exposedsurface treated by a planarization process, such as chemical mechanicalpolishing (CMP) process, if necessary. The CMP process utilizes a slurryto help etch away the materials over the ILD layer 120, including theseed layer 160 and the copper-containing metal 170.

FIG. 2 is a flowchart of a method 200 of forming an interconnectstructure 100 according to various embodiments of the presentdisclosure. Also referring to FIGS. 1-8, the method 200 includes anoperation 202, in which a dielectric material layer 120 is depositedover a substrate 110. The dielectric material layer 120 may be aninterlayer dielectric (ILD) and may contain an oxide material or a low-kmaterial. The dielectric material layer 120 may be formed by, forexample, a chemical vapor deposition (CVD) processing step, a spin-onprocessing step, or combination thereof The dielectric layer 120 isprovided to isolate conductive features formed on different and/or thesame layers.

The method 200 includes an operation 204, in which an opening 125 isformed in the dielectric material layer 120. For various embodiments,there is a plurality of the openings formed in the dielectric materiallayer 120. The opening 125 may be, for example, contact openings, viaopenings, single damascene openings, dual damascene openings, orcombinations thereof The opening 125 may be formed, for example, byforming a patterned photoresist layer (not shown) over the dielectricmaterial layer 120 and using a dry-etch processing step to removeportions of the dielectric material layer 120 to define the opening 125by using the patterned photoresist layer (not shown) as a mask. Varioussuitable dry etch processes may be used. After the dry-etch processingstep, the patterned photoresist layer (not shown) is removed by, forexample, a photolithographic removal process.

The method 200 includes an operation 206, in which the opening 125 isdeposited with a first Ta barrier layer 130 having β phase. Inembodiments, the first Ta layer may be deposited by a chemical vapordeposition (CVD), physical vapor deposition (PVD), or atomic layerdeposition (ALD).

In operation 208, an α-phase inducing metal layer 140 is formed on thefirst Ta barrier layer 130. As various embodiments, the α-phase inducingmetal layer 140 is electroless-plating a metal layer selected from thegroup consisting of Cu, Cobalt (Co), Titanium (Ti), and Ruthenium (Ru).In embodiments, the α-phase inducing metal layer 140 may be in conformaldeposition with substantially uniform thickness over the entire surfaceof the the first Ta barrier layer 130, or only the bottom the first Tabarrier layer 130.

In operation 210, a second Ta layer is deposited on the α-phase inducingmetal layer 140 and thus having α phase 150. In embodiments, the secondTa layer may be deposited by a CVD, PVD, or ALD.

Further, the method 200 includes an operation 212, in which a seed layerof a first copper-containing metal 160 is formed on the second Tabarrier layer 150 through a process such as an electroplating process.

In operation 214, the opening 125 a second copper-containing metal isfilled with a metal material. The metal material may be formed in asuitable deposition process. Electroplating processes are generally usedto deposit copper because such processes have better gap fillingcapability as compared to PVD or CVD. The PVD techniques include, forexample, various evaporation and sputtering techniques, such as DCand/or RF plasma sputtering, bias sputtering, magnetron sputtering, ionplating, or ionized metal plasma sputtering. PVD processes generallyproduce non-conformal deposition due to their anisotropic anddirectional nature. The CVD techniques include, for example, thermalCVD, plasma enhanced CVD, low pressure CVD, high pressure CVD, andmetal-organo CVD. CVD processes most frequently produce conformaldeposition with substantially uniform thickness over the entire surface,including over the field and the bottom and sidewall surfaces of theopenings.

The method 200 may further includes a chemical-mechanical (CMP) processan electropolishing step, a dry etch step, or combinations thereof,which is performed to remove portions of the metal material over thedielectric layer. The second Cu-containing metal and the seed layer ofthe first Cu-containing metal are partially removed by a CMP processingstep, an electropolishing step, a dry etch step, or combinations thereofA multi-step CMP process may be required to remove the secondCu-containing metal 170, the seed layer 160 and the Ta barrier layers150/130 formed over the surface of the dielectric layer 120 a. In short,a separate CMP step is used to remove the Ta barrier layer formed overthe dielectric layer 120 for isolating two adjacent contacts, viasand/or damascenes.

In FIG. 3, a substrate 110 is provided with a dielectric material layer120 thereover. Referring to the operation 202 of FIG. 2, the substrate110 is a silicon substrate doped with either a P-type dopant such asboron, or doped with an N-type dopant such as phosphorous or arsenic.The substrate 110 may alternatively include other elementarysemiconductors such as germanium and diamond. The substrate 110 mayoptionally include a compound semiconductor and/or an alloysemiconductor. Further, the substrate 110 may include an epitaxial layer(epi layer), may be strained for performance enhancement, and mayinclude a silicon-on-insulator (SOI) structure. The dielectric materiallayer 120, also referred to as an interlayer dielectric (ILD) layer. TheILD layer 120 may include dielectric materials such as oxide, nitride, alow-k dielectric material, or another suitable material. The ILD layer120 may include one or more dielectric materials and/or one or moredielectric layers.

In FIG. 4, an opening 125 is formed through the dielectric materiallayer 120 to the substrate 110. Referring to the operation 204, in theformation of the opening 125, a layer of photoresist (not shown) isformed over the ILD layer 120 by a suitable process, such as spin-oncoating, and patterned to form a patterned photoresist feature by alithography patterning method. The patterned photoresist feature canthen be transferred using a dry etching process to etch the opening 125for contacts through the dielectric material layer 120. The photoresistlayer is stripped thereafter. The opening 125 is configured to be filledwith conductive feature to provide electrical connections betweenmicroelectronic components of a semiconductor device (for example,transistor devices) and external devices.

Referring to FIG. 5 and the operation 206 of FIG. 2, a first tantalum(Ta) barrier layer 130 is formed over the opening 125 as well as thedielectric material layer 120 through a suitable deposition process,such as physical vapor deposition (PVD), chemical vapor deposition(CVD), atomic layer deposition (ALD), combination thereof, or anothersuitable process. The first Ta barrier layer 130 may have acrystallographic structure of beta (β phase, which shows high contactresistance. For various embodiments of the present disclosure, the firstTa barrier layer 130 with β phase has a thickness between about 10 and100 angstroms. As embodiments of the present disclosure, the first Tabarrier layer 130 with β phase has a thickness between about 50 and 85angstroms.

Referring to FIG. 6 and the operation 208 of FIG. 2, an alpha (α)-phaseinducing metal layer is deposited on the first Ta barrier layer 130through a suitable deposition process like an electroplating process, orthat for the first Ta barrier layer 130. As embodiments, the α-phaseinducing metal layer is formed at least over the first Ta barrier layer130 at a bottom of the opening 125 (i.e. the exposed surface of thesubstrate 110). The α-phase inducing metal layer 140 is so named for thelayer is introduced on the first Ta barrier layer in order to induce theformation of a subsequently deposited Ta barrier layer having a primarycrystallographic structure of α phase, which has a lower Rc than that ofthe β-phase Ta. The candidate materials are those capable of inducingthe formation of the α-phase Ta barrier layer. For example, the α-phaseinducing metal layer is formed from a metal selected from the groupconsisting of Cu, Cobalt (Co), Titanium (Ti), and Ruthenium (Ru). Forvarious embodiments of the present disclosure, the alpha-phase inducingmetal layer has a thickness between about 5 and 60 angstroms. Asembodiments, the alpha-phase inducing metal layer has a thicknessbetween about 15 and 50 angstroms.

In FIG. 7 and the operation 210 of FIG. 2, a second Ta barrier layer 150is deposited over the α-phase inducing metal layer 140. For variousembodiments of the present disclosure, the second Ta barrier layer 150with α phase has a thickness between about 5 and 60 angstroms. Asembodiments of the present disclosure, the first Ta barrier layer 130with β phase has a thickness between about 5 and 20 angstroms.

Usually, a thin copper layer is deposited over the barrier layer toserve as the seed layer. In FIG. 8 and the operation 212 of FIG. 2, aseed layer 160 is deposited over the second Ta barrier layer 150. Theseed layer 160 may be formed by, for example, a PVD process, a CVDprocess, an ALD process, an electroplating, an electroless plating or acombination thereof The seed layer 160 is needed to provide theconductivity for the electrochemical deposition reaction and to providenucleation sites for the subsequent copper electroplating. The seedlayer 160 is made of a first copper-containing metal selected from thegroup consisting of copper (Cu), copper magnesium (CuMg), copperaluminum (CuAl), copper manganese (CuMn), copper titanium (CuTi), coppersilicon (CuSi), copper tungsten (CuW), copper tantalum (CuTa), copperzirconium (CuZr), copper molybdenum (CuMo), and combinations thereof.

Referring to FIG. 9 and the operation 214 of FIG. 2, a secondcopper-containing metal 170 is filled in the opening 125. The secondcopper-containing metal is a metal selected from the group consisting ofCu, CuMg, CuAl, CuMn, CuTi, CuSi, CuW, CuTa, CuZr, CuMo, andcombinations thereof.

Based on an X-ray diffraction (XRD) analysis, a nanocrystallinemicrostructure of the barrier layer 150 was identified with α-phase Tastructure. The predominant (110) oriented α-phase Ta barrier layer 150is characterized by an x-ray diffraction peaks at 2Θ=38°. The XRDanalysis indicates that a α-phase Ta layer is successfully induced byand formed on the α-phase inducing copper layer, which is introducedfirst on the β-phase Ta barrier layer.

Normally, with the PVD process, a conductive feature in an interconnectwith a Ta barrier layer of a thickness of 200 angstroms has a nearly 20%lower Rc than that of conventional the interconnect structure with onlythe β-phase Ta barrier layer. 20%.

Given the above, according to various aspects of the present disclosure,an interconnect structure includes a substrate, a dielectric materiallayer on the substrate, and a conductive feature in the dielectriclayer. The conductive feature has a Cu-containing metal, an alpha-phaseTa barrier layer at least partially, peripherally surrounding theCu-containing metal, an α-phase inducing metal layer peripherallysurrounding the α-phase Ta barrier layer and a β-phase Ta barrier layerperipherally surrounding the α-phase inducing metal layer. Theinterconnect structure may further includes another conductive featureoverlying or underlying the conductive feature.

In embodiments, the α-phase Ta barrier layer has a thickness of betweenabout 5 and about 60 angstroms. The α-phase inducing metal layer mayhave a thickness between about 5 and 60 angstroms. The β-phase Tabarrier layer may have a thickness of between about 10 and about 100angstroms. As various embodiments, the Cu-containing metal may beselected from the group consisting of Cu, copper magnesium (CuMg),copper aluminum (CuAl), copper manganese (CuMn), copper titanium (CuTi),copper silicon (CuSi), copper tungsten (CuW), copper tantalum (CuTa),copper zirconium (CuZr), copper molybdenum (CuMo), and combinationsthereof.

In embodiments, the α-phase inducing metal layer may be disposed atleast over the β-phase Ta barrier layer at a bottom of the opening. Theα-phase inducing metal layer may be made of a metal selected from thegroup consisting of Cu, Cobalt (Co), Titanium (Ti), and Ruthenium (Ru).

According to various aspects of the present disclosure, an integratedcircuit device includes a substrate, a plurality of inter-layerdielectric layer on the substrate, and a plurality of conductivefeatures each has a β-phase Ta barrier layer, an α-phase inducing metallayer on the β-phase Ta barrier layer, an α-phase Ta barrier layer onthe α-phase inducing metal layer, and a Cu-containing metal on theα-phase Ta barrier layer. The respective conductive features arecorrespondingly in the respective dielectric layers.

According to various aspects of the present disclosure, a method forforming an interconnect structure includes the following operations. Adielectric material layer is deposited on a substrate. An opening in thedielectric layer is formed to expose an underlying conductive material.Also, a conductive feature is formed. In the forming the conductivefeature, a first Ta barrier layer is deposited in the opening; anα-phase inducing metal layer is formed on the first Ta barrier layer; asecond Ta barrier layer is deposited on the α-phase inducing metallayer; and the opening is filled with a second Cu-containing metal

The embodiments of the present disclosure discussed above haveadvantages over existing structures and methods. The α-phase inducingmetal layer formed at least over the first Ta barrier layer at a bottomof the opening, which induces the formation of a subsequently depositedTa barrier layer having the primary crystallographic structure of αphase having a lower Re than that of the β-phase Ta barrier layer. It isunderstood, however, that other embodiments may have differentadvantages, and that no particular advantage is required for allembodiments.

The foregoing has outlined features of several embodiments so that thoseskilled in the art may better understand the detailed description thatfollows. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions andalterations herein without departing from the spirit and scope of thepresent disclosure.

1. An interconnect structure, comprising: a substrate; a dielectricmaterial layer on the substrate; and a conductive feature in thedielectric layer, the conductive feature having: a copper(Cu)-containing metal; an alpha (α)-phase tantalum (Ta) barrier layer atleast partially, peripherally surrounding the Cu-containing metal; anα-phase inducing metal layer peripherally surrounding the α-phase Tabarrier layer; and a beta (β)-phase Ta barrier layer peripherallysurrounding the α-phase inducing metal layer.
 2. The interconnectstructure of claim 1, wherein the α-phase inducing metal layer has athickness of between about 5 and about 60 angstroms.
 3. The interconnectstructure of claim 1, wherein the α-phase Ta barrier layer has athickness of between about 5 and about 60 angstroms.
 4. The interconnectstructure of claim 1, wherein the β-phase Ta barrier layer has athickness of between about 10 and about 100 angstroms.
 5. Theinterconnect structure of claim 1, wherein the Cu-containing metal isselected from the group consisting of Cu, copper magnesium (CuMg),copper aluminum (CuAl), copper manganese (CuMn), copper titanium (CuTi),copper silicon (CuSi), copper tungsten (CuW), copper tantalum (CuTa),copper zirconium (CuZr), copper molybdenum (CuMo), and combinationsthereof.
 6. The interconnect structure of claim 1, wherein the α-phaseinducing metal layer is at least over the β-phase Ta barrier layer at abottom of an opening.
 7. The interconnect structure of claim 1, furthercomprising another conductive feature overlying or underlying theconductive feature.
 8. The interconnect structure of claim 1, whereinthe α-phase inducing metal layer is made of a metal selected from thegroup consisting of Cu, Cobalt (Co), Titanium (Ti), and Ruthenium (Ru).9. An integrated circuit device, comprising: a substrate; a plurality ofinter-layer dielectric layer on the substrate; and a plurality ofconductive features, the respective conductive features correspondinglyin the respective dielectric layers, each the conductive feature having:a β-phase Ta barrier layer; an α-phase inducing metal layer on theβ-phase Ta barrier layer; an α-phase Ta barrier layer on the α-phaseinducing metal layer; and a Cu-containing metal on the α-phase Tabarrier layer. 10-20. (canceled)
 21. The interconnect structure of claim1, wherein the Cu-containing metal comprises a second copper-containingmetal and a seed layer peripherally surrounding the secondcopper-containing metal.
 22. The interconnect structure of claim 21,wherein the seed layer is different from or same as the secondcopper-containing metal in composition.
 23. The integrated circuitdevice of claim 9, wherein the α-phase inducing metal layer has athickness of between about 5 and about 60 angstroms.
 24. The integratedcircuit device of claim 9, wherein the α-phase Ta barrier layer has athickness of between about 5 and about 60 angstroms.
 25. The integratedcircuit device of claim 9, wherein the β-phase Ta barrier layer has athickness of between about 10 and about 100 angstroms.
 26. Theintegrated circuit device of claim 9, wherein the Cu-containing metal isselected from the group consisting of Cu, copper magnesium (CuMg),copper aluminum (CuAl), copper manganese (CuMn), copper titanium (CuTi),copper silicon (CuSi), copper tungsten (CuW), copper tantalum (CuTa),copper zirconium (CuZr), copper molybdenum (CuMo), and combinationsthereof.
 27. The integrated circuit device of claim 9, wherein theα-phase inducing metal layer is at least over the β-phase Ta barrierlayer at a bottom of an opening.
 28. The integrated circuit device ofclaim 9, wherein other conductive features are overlying or underlyingthe conductive feature.
 29. The integrated circuit device of claim 9,wherein the α-phase inducing metal layer is made of a metal selectedfrom the group consisting of Cu, Cobalt (Co), Titanium (Ti), andRuthenium (Ru).
 30. The integrated circuit device of claim 9, whereinthe Cu-containing metal comprises a seed layer and a secondcopper-containing metal on the seed layer.
 31. The integrated circuitdevice of claim 30, wherein the seed layer is different from or same asthe second copper-containing metal in composition.